1. Field of the Invention
The present invention relates to a method of forming a MOS transistor, and particularly to a method of forming a MOS transistor having an improved short channel effect.
2. Description of the Prior Art
Field effect transistors (FETs) are important electronic devices in the fabrication of integrated circuits, and as the size of the semiconductor device becomes smaller and smaller, the fabrication of the transistors is also improved and constantly enhanced for fabricating transistors with smaller sizes and higher quality.
In the conventional method of fabricating transistors, a gate structure is first formed on a substrate, and a lightly doped drain (LDD) is formed on the two corresponding sides of the gate structure. Next, a spacer is formed on the sidewall of the gate structure and an ion implantation process is performed to form a source/drain region within the substrate by utilizing the gate structure and spacer as a mask. Finally, an anneal process is performed.
Refer to FIG. 1, a schematic diagram showing a conventional field effect transistor. As shown in FIG. 1, a gate structure 106 having a gate dielectric layer 102 and a gate electrode 104 is first formed on a substrate 100. Next, an ion implantation process is performed to form a lightly doped drain 110 in the substrate 100. Next, a spacer 108 is formed on the sidewall of the gate structure 106 and another ion implantation is performed to form a source/drain region 112 in the substrate 100. Subsequently, a rapid thermal process (RTP) is performed to obtain a FET.
With the device scaling down, it's difficult to control the junction depth (Xj) and also reduce the access resistance. The short channel effect (SCE) noticeably depends on the junction depth. The junction depth for the source/drain of a transistor must be reduced to avoid the short channel effect of the MOS arisen from the shrinkage of the MOS size to increase the integration of the device. A lot of papers have demonstrated many approaches to improve the pFET SCE. But from 65 nm node and beyond, the conventional As (arsenic) implantation and spike RTP can hardly meet the nFET SCE requirement.
From the above viewpoint, the shallower as-implant depth by heavy ions or less diffusion activation tool is needed. Unfortunately the advanced activation tools (for example, flash or laser anneal) are under development and not mature.
A method of manufacturing a PMOS transistor has been disclosed to implant fluorine in a source/drain extension region or source/drain region to be with the dopants thereat together. The diffusion for the dopants can be improved during a subsequent annealing process, to alleviate the SCE.
However, because transistors with smaller sizes and higher quality are constantly desired, a method of manufacturing an FET with an improved SCE and a good junction profile is still needed.